Locating a virtual address (VA) in real storage is automatically done in a computer system through use of the dynamic address translation (DAT) process. Then a system's real memory space can be allocated independently of how any virtual address space (VAS) is used. Thus use of virtual storage to allow free use of any number of contiguous and large VAS units of up to 2 GB each allows real memory to be allocated without concern about where the real storage is located. Dividing real storage into fixed size units (e.g. 4 KB pages) having the same access time (regardless of where in real storage they are located) allows any VAS to be mapped into real storage as a set of non-contiguous pages scattered anywhere in real storage without affecting system performance in the use of any VAS. This random access characteristic of dynamic RAM (DRAM) or static RAM (SRAM) storage distinguishes its access time from DASD storage in which access time deteriorates due to the intervention of mechanical spin time and arm movement time.
It is known that the size of the virtual address used by a system controls the size of virtual address spaces (VASs) usable by the system, and that the maximum VAS size is equal to 2 to a power equal to the number of bit positions in the address size. For example, an address with 31 bits enables a VAS of 2**31 bytes.
A VAS is a sequence of virtual addresses (preferably starting from zero up to an upper limit) which conveniently allows a program to locate instructions and/or data without concern for how computer hardware actually locates the instructions or data in a real memory. The software uses the virtual addresses, while the hardware stores or retrieves the content of these virtual addresses in real memory and avoids problems, such as memory fragmentation and discontiguous real storage management, and passes storage management from application programs to the system control program.
It is also known that increasing the virtual address size increases the VAS size, which then contains more bytes of information (data and/or instructions) because of the greater number of available byte addresses.
The maximum size of a virtual address (VA) for which a system is designed is not allowed to be exceeded in the operation of a machine. Increasing the address size above a current maximum size can cause difficult problems to compatibility with prior programs, and to the design of future programs and data bases for a computer system. When the amount of data that should be concurrently addressable exceeds the maximum size of a VAS, the program must contain steps to manipulate multiple VASs.
Some computer systems put operand addresses within instructions, and if the address size were to be increased all instructions would have to be redesigned for the larger address size. Other computer architectures do not suffer from this incompatibility up to some address size limit, such as the IBM S/370 because it does not have its instructions directly contain instruction addresses; but instead the storage operands within the instructions specify general purpose registers (GPRs), containing base (B) and index (X) values, and an address component (D). The well known address arithmetic operation on the B,X,D operand specification obtains the operand address. The S/370 operand architecture is carried over into the IBM ESA/390 system.
The B,X,D operand specification can support any address size providing any VAS size as long as the GPR size corresponds to the maximum address size. Thus, having a hardware GPR size of 32 bits in a particular hardware model results in a current maximum address size of 31 bits. The 32nd bit (i.e. bit 0 of each address) is currently reserved for address interpretation, required by a few instructions supported by the system. Thus, the 32 bit size of GPRs participating in the B,X,D address arithmetic for operand data results in a 31 bit maximum effective logical address size. And the 31 bit address size currently results in a 2 GigaByte (GB) virtual address space (i.e. 2**31) limit.
Hence, it was obvious that increasing the size of the GPRs would allow an increase in the size of the virtual addresses used for accessing operand data, such as by increasing GPR size to 64 bits from their current 32 bit size to increase the virtual address size to 2**63 or 2**64 bytes. Then a corresponding increase may be desired in the size of instruction addresses (e.g. to 63 or 64 bits from 31 bits) in the machine's PSW (program status word).
However, controlling how to handle an increase in the virtual address size is not obvious, and is the object of the invention in this application.
Although the previous virtual address size of 31 bits has been a practical limit on the maximum size of each VAS (virtual address space) in the IBM S/370 systems, the number of VASs usable by a single program was dramatically increased from one per system user to thousands per user by the ESA/370 access register (AR) architecture. ARs allow easy access to data in plural VASs by a single program, wherein data can easily be accessed in plural VASs, which may be different from the VAS(s) containing the instructions controlling the data. ARs were disclosed and claimed in U.S. Pat. No. 4,355,355 (Butwell et al) for accessing multiple virtual address spaces. An AR specified a VAS by specifying its segment table designation (STD). A family of 2 GB address spaces was provided to any ESA/370 program using the AR teaching of U.S. Pat. No. 4,355,355.
U.S. Pat. No. 4,979,098 (Baum et al) enabled use of a central depository of STDs in a system by using an AST (address-space-number second table), and improved the security for VASs designated by ARs by putting indirection between the content of an AR and its specified STD (defining the VAS). The valid ASN second table entries (ASTEs) in the AST (ASN second table) contained the STDs defining all virtual address spaces currently recognized by the system. Having a single table defining all virtual spaces in a system allows central control over their creation, deletion, and access authority.
Security is provided by the indirection between each AR and its STD that was obtained by using an access list (AL) having pointers to a subset of ASTEs containing the required STDs. The AL was located by a control register field. The AR was loaded with an access list entry token (ALET) for accessing the required VAS, instead of loading the AR with the required STD (which would prevent the control program from changing the location of the segment table). Nevertheless, the AR content (the ALET) still represented the STD. And non-supervisory users of a system are permitted to load and manipulate ALETS in ARs as if they are STDs to control the use of VASs in the system.
Each AL (available to a given user) must have its AL entries (ALEs) initialized to contain pointers to the ASTEs containing STDs that are to correspond to the ALETs available to a given user.
The ALET in an AR contains an access-list-entry-number (ALEN), an access-list-entry sequence number (ALESN) and a primary list bit (P). The ALEN indexes into the AL for selecting a required ALE (access list entry). The ALE content points to a particular ASTE (ASN second table entry) which contains the STD represented by the AR.
The process of following an ALET's indirection path from the AR to its STD is called the AR translation (ART) process, which includes validity and authority checking. The validity checking uses the ALESN (ALE sequence number) in the ALET to protect the program from inadvertently attempting to use an ALE after it has been reassigned to a different STD (the same ALET with a different ALESN value), since an equal-comparison in needed to obtain access. And if the ALESN fields compare-equal, then ASTESN (ASTE serial number) fields in the ALE and in the ASTE (ASN Second Table Entry) are compared during the ART (AR translation) process and they also must be equal to enable access to the STD in the ASTE. The ASTESN (ASTE sequence number) protects the system where reassignment of an ASTE has occurred from one STD to another, for example.
The above stated acronyms are defined in pages 5-23 thru 5-53 in the prior publication entitled "IBM Enterprise Systems Architecture/370 Principles of Operation" (form no. SA22-7200-0).
The ART process is completed when it accesses the STD corresponding to the ALET in the AR. An STD is comprised of a STO (segment table origin) for locating a segment table (ST), and a STL (segment table length). A respective page table is located through each ST entry (STE).
The ART process is speeded up by using an ALB (ART lookaside buffer) to store the results of an ART operation, i.e. the ALET and the ALET's resulting STD. This ALB entry is accessed by the ART process the next time the ALET in the AR is accessed to more quickly obtain its STD.
After the ART process obtains the required STD, the conventional DAT (dynamic address translation) process is started for the VA, for which the VA indexes into the addressed ST to find a page table (PT), and the VA then indexes into the PT to obtain a required page table entry (PTE) containing the page frame real address (PFRA) that represents the translation of the VA (which locates the required page in real storage).
Accordingly, an ALET (through its STD) locates a segment table that represents a 2 GigaByte (GB) virtual address space, which is accessed for translating 31 bit virtual addresses to real addresses in the ESA/390 architecture.
Nevertheless, the use of the AR architecture effectively exceeds the 31 bit virtual address limit (while using 32 bit GPRs) by providing a virtual extension in the AR associated with the B-GPR specified in the current B,X,D operand field of a data address. The 31 bit address plus the AR extension are used to represent a virtual address of up to 48 bits (the 31 bit VA+the 16 bit ALEN+1 P bit).
Thus, the 32 bit GPR size is not changed by the AR architecture, when it enables the 31 bit VA size to support a family of up to 2**16=65536 virtual address spaces, in which the size of each virtual address space is 2**31=2 GigaBytes. This resulted in each application program having a total virtual space capacity of 2**47 bytes of data in its maximum number of 2**16 address spaces per access list.
The ALET in an AR defines a 2 GB virtual address space. The ALET has three fields: a 16 bit index value called an ALEN, an 8 bit sequence number called an ALESN, and a primary list bit P, which selects between two access lists. The ALEN is an index into an access list (AL) to select an entry (ALE) that points to an entry in another table called an AST. The ALESN is a sequence number used to check whether the AR is to be permitted to access the ALE, and protects a program whose operation has caused reassignment of an ALE from use of an incorrect ALET. An ASTESN field in an ALE is used during the ART process to check whether or not an AR is to be permitted to access an ASTE through the specified ALE. Access is permitted only if the content of the ASTESN field of the ALE matches the ASTESN field in the ASTE. A 31 bit address in an ALE locates the ASTE containing the required STD. The ASTESN field of an ASTE can be changed to prevent a match, thereby withdrawing authority from ALEs currently addressing it, and requiring that they obtain authorization before their next access is allowed to that ASTE.
U.S. Pat. No. 4,355,355 (Butwell et al) discloses access registers (ARs) for enabling ease of use of a plurality of address spaces by an application program.
U.S. Pat. No. 4,979,098 (Baum et al) discloses and claims access register translation (ART) using an indirection through an access list (AL). A token (ALET) is provided in an AR to represent a segment table designation (STD). An index (ALEN) field in the AR accesses an entry in the AL to obtain a pointer to the ASTE containing the STD. A pair of sequence numbers (ALESN and ASTESN) variously placed in the ALET, in the ALE and in the ASTE provide authority control over the accessing of the STD. The STD accessing used one of plural ALs selected by the setting of a P bit also in the ALET in the AR. With this patent, a program using ARs has access to a family of virtual address spaces through the ALETs provided to the program to represent the address spaces available to the program.
U.S. Pat. No. 4,679,140 (Gotou et al) describes increasing the GPR size from 32 up to 64 bits for generating 48 and 64 bit addressing. A mode register is associated with each GPR to indicate if it contains a 32, 48 or 64 bit address when it is being used as a B or X register, to maintain downward compatibility with 32 bit addressing. A 64 bit address arithmetic circuit is used with the 64 bit GPRs and is controlled by the mode bits which determine whether 32, 48 or 64 bit arithmetic is to be used. This Gotou patent does not disclose the large virtual address concepts taught in the subject application.
U.S. Pat. No. 4,868,740 (Kagimasa et al, 1987 priority) discloses and claims a program status word (PSW) extended address mode for 48 bit addresses, as an alternative for 31 bit addresses. This Kagimasa patent does not disclose the large virtual address concepts taught in the subject application.
Japanese application 63-305443 filed Jun. 8, 1987 discloses virtual addresses having a high-order family (F) field used as an index into a table of STOs to find a required STO. This Japanese application does not disclose the large virtual addressing concepts taught in the subject application.
Concurrent U.S. patent specification Ser. No. 07/754,810, filed Sep. 4, 1991, entitled "Method and Means For Addressing a Very Large Memory", and assigned to the same assignee as this application, does not disclose the invention of the subject application, but discloses and claims how a small real address (e.g. 31 bit) for addressing a small real memory (under 2 GB) can be converted into a large real address (i.e. 64 bits) for addressing a large memory (over 2 GB), while maintaining upward compatibility for old S/370 programs. It also discloses and claims how the DAT and/or ART process for small VAs can be used in the generation of large real addresses (LRAs) provided as the translations of the small VAs.
U.S. patent specification Ser. No. 07/754,810 generates an LRA by concatenating a predetermined extender which defines a 2 GB section of the real memory. A 2 GB memory boundary is crossed (when the conventional 32 bit address generating adder using 31 bit B and X general register values and a 12 bit displacement value) overflows into its highest order bit position zero, which increments the extender by one. This may be done by using the overflow bit content to interrupt the current program and invoke the control program to perform this incrementing.